A floating gate transistor is a field effect transistor having a structure similar to a conventional MOSFET (metal oxide semiconductor field effect transistor). Floating gate transistors are used in flash memory devices that typically store information in an array of memory cells made using the floating gate transistors. Flash memory devices are non-volatile storage devices that can be electrically erased and reprogrammed and they are commonly used in memory cards, USB flash drives and solid-state drives for general storage and transfer of data between computers and other digital products.
Floating gate MOSFETs are distinguished from conventional MOSFETs because the floating gate transistor includes two gates instead of one. In addition to an upper control gate, a floating gate transistor includes an additional floating gate beneath the control gate and above the transistor channel but completely electrically isolated by an insulating layer such as an oxide layer that completely surrounds the floating gate. This electrically isolated floating gate creates a floating node in DC with a number of inputs or secondary gates such as the control gate, formed above the floating gate and electrically isolated from it. These secondary gates or inputs are only capacitively connected to the floating gate. Because the floating gate is completely surrounded by highly resistive material, i.e. the insulating layer, any charge placed on the floating gate is trapped there and the floating gate remains unchanged for long periods of time until the floating gate MOSFET is erased. Unless erased, the floating gate will not discharge for many years under normal conditions. Fowler-Nordheim Tunneling or other Hot-Carrier injection mechanisms may be used to modify the amount of charge stored in the floating gate, e.g. to erase the floating gate. The erase operation is therefore critical to the operation of floating gate transistors.
The default state of an NOR (“Not Or” electronic logic gate) flash cell is logically equivalent to a binary “one” value because current flows through the channel under application of an appropriate voltage to the control gate when charge is stored in the floating gate. Such a flash cell device can be programmed or set to binary “zero” by applying an elevated voltage to the control gate.
To erase such a flash cell, i.e. resetting it to the “one” state, a large voltage of the opposite polarity is applied between the control gate and the source causing electrons to exit the floating gate through quantum tunneling. In this manner, the electrical charge is removed from the floating gate. This tunneling necessarily takes place through the inter-gate dielectric formed between the floating gate and the control gate. The inter-gate dielectric extends over the floating gate including over the edge of the floating gate and the tunneling typically takes place through the inter-gate dielectric at the edge of the floating gate. The configuration, size and shape of the floating gate and the inter-gate dielectric have a significant impact on tunneling and the ability to erase the flash cell.
The shape and thickness of the inter-gate dielectric is critical to the tunneling and overall operation of the floating gate transistor. The shape and integrity of the floating gate is also critical to the tunneling and overall operation of the floating gate transistor. When the inter-gate dielectric formation process includes oxidizing the floating gate, i.e. forming an oxide layer at the expense of the floating gate, the floating gate can be completely consumed and this destroys the structural integrity and the operational characteristics of the floating gate and therefore the floating gate transistor and the flash cell that includes the floating gate transistor. This can destroy device functionality. Conventional methods and structures for forming floating gate transistors tend to be uncontrolled and to consume too much of the floating gate, and can, at times, consume the entire thickness of the floating gate.
Conventional methods and structures for forming floating gate transistors face challenges to address the above and other concerns and to prevent the above shortcomings and limitations.